In high-speed design, the stackup = the foundation of signal quality.

More than 80% of issues such as impedance fluctuation, crosstalk, EMI, and improper return paths come from stackup mistakes.

Below are the 8 most critical stackup principles in high-speed PCB design. Each is closely related to impedance control and mass-production stability.

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01. Signal Layers Must Be Adjacent to a Reference Plane (Preferably GND)

If a high-speed signal is too far from its reference plane, it will cause:

• Large impedance deviation, difficult to control

• Longer return path → increased EMI

• Layer-to-layer variation → poor consistency in mass production

Best practices:

• Each high-speed signal layer should be adjacent to a solid and continuous GND plane

• Avoid crossing slots, splits, or isolated copper islands

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02. Avoid Three Consecutive Signal Layers (S-S-S)

Stacking multiple signal layers together leads to:

• Increased interlayer crosstalk

• Broken reference planes

• Impedance jumps from layer to layer

Recommended structures:

• S–G–S (classic and most stable)

• S–PWR–S (power can be a secondary reference, but inferior to GND)

Especially for 8-layer and 10-layer boards, avoiding three consecutive signal layers is a key rule of thumb.

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03. Keep a Controlled Dielectric Thickness Between Power and Ground

In high-speed design, a smaller PWR–GND spacing results in:

• Higher plane capacitance

• Lower high-frequency noise

• Better power integrity

Recommended:

• Keep spacing around 3–6 mil

• For CPU/DDR areas, use thin dielectric PWR–GND pairs

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04. Minimize High-Speed Routing on Top and Bottom Layers

Outer-layer routing is more susceptible to:

• Higher EMI

• Larger impedance variation

• Effects from pads, solder mask, and surface finish

Best practices:

• Route high-speed differential pairs in inner layers (stripline)

• Use outer layers for low-speed, control signals, or non-timing-critical lines

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05. Thinner Dielectric Is Not Always Better—It Must Match the Trace Width

Many designers push for 2–3 mil dielectric for high-speed signals, but this introduces issues:

• Trace width becomes too narrow to fabricate

• Impedance is harder to stabilize

• Resin flow and prepreg control become difficult

• Higher manufacturing cost

Correct concept:
Impedance is determined by the stackup, not by blindly reducing dielectric thickness.

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06. Differential Pairs Require a Stable Dielectric Environment

Differential impedance depends on three main factors:

• Trace width

• Trace spacing

• Dielectric thickness & DK value

If the dielectric environment is inconsistent (e.g., top-layer DK varies due to solder mask), it will cause:

• Differential impedance deviation

• Eye-diagram degradation

• Timing skew

Place differential pairs in inner layers (stripline with dual reference planes) for best consistency.

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07. Every Signal Layer Must Have Its Own Reference Plane

Common mistakes:

• Using a PWR plane as reference when that power is not related to the signal

• No return-path stitching vias when a signal changes layers

Correct approach:

• Add GND stitching vias whenever a signal changes layers

• The core rule: “Where the signal goes, the return path follows.”

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08. High-Speed Stackups Must Be Manufacturable and Impedance-Friendly

To ensure impedance can be controlled, the following must be stable:

• Dielectric thickness

• Copper thickness

• Line geometry

• Repeatable stackup structure

Recommendations:

• Use mature, industry-proven materials (IT180A, TU872, Rogers series, etc.)

• Avoid pushing extreme parameters (1.5 mil core, 1 mil trace width, etc.)

The ultimate goal:
Stable mass production, compliant impedance, and controllable cost.

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Example: A Common 8-Layer High-Speed Stackup (Suitable for DDR4/PCIe)

(Example only; adjust based on your company’s material system.)

1. L1: Signal (low-speed control/interface)

2. L2: GND

3. L3: High-speed signal (DDR/PCIe differential pairs)

4. L4: PWR

5. L5: High-speed signal (DDR/PCIe differential pairs)

6. L6: GND

7. L7: Low-speed signal

8. L8: GND or large copper ground plane

Advantages:

• Layers 3/5 are shielded inner high-speed layers

• Layers 2/6 provide dual reference planes

• Stable impedance and easy for volume production

• Easier EMI control